As is known in the art, there is trend toward miniaturization of electronic products such as mobile phones, tablets, digital cameras, and the like. Consequently, there has been a trend in semiconductor device manufacturing towards smaller and more densely packed semiconductor structures. This has resulted in a demand for semiconductor packages which are relatively low loss, lightweight structures and which support increased electronic capabilities (e.g., increased density, mobility and extended operational life) in miniaturized electronic products demanded by both military and commercial customers alike.
The foregoing trend and demand, drives a need for multi-layer semiconductor structures (also commonly referred to as three-dimensional (3-D) integrated circuits (ICs)), semiconductor structures in which a number of individual semiconductor structures are both mechanically and electrically coupled. One example multi-layer semiconductor structure is described in U.S. Pat. No. 7,067,909 entitled “Multi-layer integrated semiconductor structure having an electrical shielding portion,” which is assigned to the assignee of the present disclosure and incorporated herein by reference in its entirety.
In fabricating multi-layer semiconductor structures, such as that which is described in the above-reference U.S. Pat. No. 7,067,909, for example, individual semiconductor structures are typically stacked, bonded (La mechanically coupled) and electrically coupled using one or more interconnects. Conventional interconnects include, for example, solder balls, self-aligned contact pads, bond wires, conductive pads and the like. Such interconnects, have an associated pitch. Typically, data and power signals (e.g., power/ground connections) flow through interconnects of the individual semiconductor structures.
While it is desirable to reduce interconnect pitch, a competing requirement is that relatively simple and cost effective approaches are needed in order for such to be practical.